R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 828

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 3.00 Mar. 14, 2006 Page 790 of 804
REJ09B0104-0300
Item
Section 15 A/D Converter
15.1 Features
Figure 15.2 Block Diagram of A/D
Converter (Unit 1/AD_1)
15.3.2 A/D Control/Status
Register (ADCSR)
•
15.3.2 A/D Control/Status
Register (ADCSR)
•
Section 16 RAM
Section 17 Flash Memory (0.18-
µm F-ZTAT Version)
17.7.1 Programming/Erasing
Interface Registers
(4) Flash Key Code Register
(FKEY)
Bit 7
Bit 5
Page Revision (See Manual for Details)
549
553
553
567
569
583
Added
Added
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
Amended
In scan mode, A/D conversion continues sequentially
on the specified channels until this bit is cleared to 0 by
software or a reset.
Amended
Amended
Programming/erasing time
Programming time: 3 ms (typ) for 128-byte
simultaneous programming, 23.4 µs per byte
Erasing time: 1000 ms (typ) per 1 block (64 kbytes)
Number of programming
The number of programming can be up to 100 times at
the minimum. (1 to 100 times are guaranteed.)
Amended
H'5A:
AV
AV
Flash memory version
ADTRG1
CC
SS
AN14
AN15
1
Product Classification
Programming/erasing of the flash memory is
enabled. (When FKEY is a value other than
H'5A, the software protection state is entered.)
10-bit D/A
H8SX/1527 12 kbytes
H8SX/1525 12 kbytes
RAM Size
Control circuit
RAM Addresses
H'FF9000 to H'FFBFFF
H'FF9000 to H'FFBFFF
Conversion start
trigger from the TPU
ADI1 interrupt
signal