R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 538
R5F61525
Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5F61525.pdf
(846 pages)
- Current page: 538 of 846
- Download datasheet (6Mb)
Section 13 Controller Area Network (HCAN)
13.4.6
The HCAN halt mode is provided to enable mailbox settings to be changed without performing an
HCAN hardware or software reset. Figure 13.14 shows a flowchart of the HCAN halt mode.
HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control
register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until
the bus becomes idle.
HCAN halt mode is cleared by clearing MCR1 to 0.
Rev. 3.00 Mar. 14, 2006 Page 500 of 804
REJ09B0104-0300
HCAN Halt Mode
CAN bus communication possible
Figure 13.14 HCAN Halt Mode Flowchart
Set MBCR
MCR1 = 1
MCR1 = 0
Bus idle?
Yes
No
: Settings by user
: Processing by hardware
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