R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 324
R5F61525
Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5F61525.pdf
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Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.27 TIORH_3
[Legend]
X: Don't care
Note:
Rev. 3.00 Mar. 14, 2006 Page 286 of 804
REJ09B0104-0300
Bit 3
IOA3
0
0
0
0
0
0
0
0
1
1
1
1
*
Bit 2
IOA2
0
0
0
0
1
1
1
1
0
0
0
1
When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and Pφ/1 is used as the
TCNT_4 counter clock, this setting is ignored and an input capture interrupt is not
generated.
Bit 1
IOA1
0
0
1
1
0
0
1
1
0
0
1
X
Bit 0
IOA0
0
1
0
1
0
1
0
1
0
1
X
X
TGRA_3
Function
Output
compare
register
Input
capture
register
TIOCA3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
Initial output is 0 output
Toggle output at compare match
Output disabled
Initial output is 1 output
0 output at compare match
Initial output is 1 output
1 output at compare match
Initial output is 1 output
Toggle output at compare match
Capture input source is TIOCA3 pin
Input capture at rising edge
Capture input source is TIOCA3 pin
Input capture at falling edge
Capture input source is TIOCA3 pin
Input capture at both edges
Capture input source is channel 4/count clock
Input capture* at TCNT_4 count-up/count-down
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