R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 230

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
(2)
In single address mode, data of one byte, one word, or one longword is transferred at a single
transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the
CPU are executed in the bus released cycles.
In figure 7.34, the TEND signal output is enabled and data is transferred in bytes from the external
8-bit 2-state access space to the external device in single address mode (write).
Rev. 3.00 Mar. 14, 2006 Page 192 of 804
REJ09B0104-0300
Single Address Mode (Write and Cycle Stealing)
B
Address bus
HHWR, HLWR
LLWR
DACK
TEND
Figure 7.34 Example of Transfer in Single Address Mode (Byte Write)
released
Bus
DMA write
cycle
released
Bus
DMA write
cycle
released
Bus
DMA write
cycle
released
Bus
DMA write
Last transfer
cycle
cycle
released
Bus