R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 172

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 7 DMA Controller (DMAC)
• Address update can be selected from fixed address, offset addition, and increment or
• Word or longword data can be transferred to an address which is not aligned with the
• Two types of interrupts can be requested to the CPU
Rev. 3.00 Mar. 14, 2006 Page 134 of 804
REJ09B0104-0300
Note: * An external request and single address mode are not supported by the H8SX/1520
decrement by 1, 2, or 4
Address update by offset addition enables to transfer data at addresses which are not placed
continuously
respective boundary
Data is divided according to its address (byte or word) when it is transferred
A transfer end interrupt is generated after the number of data specified by the transfer counter
is transferred. A transfer escape end interrupt is generated when the remaining total transfer
size is less than the transfer data size at a single transfer request, when the repeat size of data
transfer is completed, or when the extended repeat area overflows.
Group.

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