R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 65
R5F61525
Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5F61525.pdf
(846 pages)
- Current page: 65 of 846
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2.3
The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes. It is recommended
that the mode be set according to the bus width of the memory in which a program is stored. The
instruction-fetch mode setting does not affect operation other than instruction fetch such as data
accesses.
Note: In the H8SX/1520 Group, an instruction is fetched in 32-bit mode.
2.4
Figure 2.8 shows a memory map of the H8SX CPU. The address space differs depending on the
CPU operating mode.
H'0000
H'FFFF
Normal mode
Instruction Fetch
Address Space
Program area
Data area
(64 kbytes)
H'000000
H'007FFF
H'FF8000
H'FFFFFF
Middle mode
Figure 2.8 Memory Map
Data area
(64 kbytes)
Program area
(16 Mbytes)
H'00000000
H'00FFFFFF
H'FFFFFFFF
Advanced mode
Rev. 3.00 Mar. 14, 2006 Page 27 of 804
Data area
(4 Gbytes)
Program area
(16 Mbytes)
H'FFFFFFFF
H'00000000
Maximum mode
REJ09B0104-0300
Section 2 CPU
Program area
Data area
(4 Gbytes)
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