R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 408

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 Watchdog Timer (WDT)
Note:
11.2.3
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,
but not by the WDT internal reset signal caused by WDT overflows.
Rev. 3.00 Mar. 14, 2006 Page 370 of 804
REJ09B0104-0300
Bit
5
4, 3
2
1
0
Bit
Bit Name
Initial Value
R/W
Note: * Only 0 can be written to this bit, to clear the flag.
*
Bit Name
TME

CKS2
CKS1
CKS0
Reset Control/Status Register (RSTCSR)
Only 0 can be written to this bit, to clear the flag.
R/(W)*
WOVF
7
0
Initial
Value
0
All 1
0
0
0
RSTE
R/W
6
0
R/W
R/W
R
R/W
R/W
R/W
R/W
—
5
0
Description
Timer Enable
When this bit is set to 1, TCNT starts counting. When this
bit is cleared, TCNT stops counting and is initialized to
H'00.
Reserved
These are read-only bits and cannot be modified.
Clock Select 2 to 0
Select the clock source to be input to TCNT. The overflow
cycle for Pφ = 20 MHz is indicated in parentheses.
000: Clock Pφ/2 (cycle: 25.6 µs)
001: Clock Pφ/64 (cycle: 819.2 µs)
010: Clock Pφ/128 (cycle: 1.6 ms)
011: Clock Pφ/512 (cycle: 6.6 ms)
100: Clock Pφ/2048 (cycle: 26.2 ms)
101: Clock Pφ/8192 (cycle: 104.9 ms)
110: Clock Pφ/32768 (cycle: 419.4 ms)
111: Clock Pφ/131072 (cycle: 1.68 s)
—
R
4
1
—
R
3
1
—
R
2
1
—
R
1
1
—
R
0
1