R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 156

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Interrupt Controller
Table 5.5
[Legend]
m: Number of wait cycles in an external device access.
5.6.5
The DMAC can be activated by an interrupt. In this case, the following options are available:
• Interrupt request to the CPU
• Activation request to the DMAC
• Combination of the above
For details on interrupt requests that can be used to activate the DMAC, see table 5.2 and
section 7, DMA Controller (DMAC).
Figure 5.6 shows a block diagram of the DMAC and interrupt controller.
Rev. 3.00 Mar. 14, 2006 Page 118 of 804
REJ09B0104-0300
Symbol
Vector fetch S
Instruction fetch S
Stack manipulation S
peripheral
On-chip
interrupt
module
IRQ
DMAC Activation by Interrupt
Interrupt request clear signal
Interrupt request
Interrupt request
Interrupt request
Number of Execution States in Interrupt Handling Routine
clear signal
h
Figure 5.6 Block Diagram of DMAC and Interrupt Controller
I
Interrupt controller
K
On-Chip
Memory
1
1
2
DMAC
select
circuit
2-State
Access
8
4
8
Select signal
8-Bit Bus
3-State
Access
12 + 4m
6 + 2m
12 + 4m
DMRSR0 TO DMRSR3
select
circuit
CPU
Object of Access
DMAC activation request signal
2-State
Access
4
2
4
External Device
DMAC request clear signal
16-Bit Bus
3-State
Access
6 + 2m
3 + m
6 + 2m
decision
Control signal
Priority
CPU interrupt request
2-State
Access
2
2
2
vector number
I, I2 to I0
32-Bit Bus
DMAC
3-State
Access
3 + m
3 + m
3 + m
CPU