R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 577

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

14.4.7
In clock synchronous communication mode, data communications are performed via three lines:
clock line (SSCK), data input line (SSI), and data output line (SSO).
(1)
Figure 14.12 shows an example of the initial settings in clock synchronous communication mode.
Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values.
Note: Before changing operating modes and communications formats, clear both the TE and RE
Figure 14.12 Example of Initial Settings in Clock Synchronous Communication Mode
Initial Settings in Clock Synchronous Communication Mode
[1]
[2]
[3]
[4]
[5]
bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0
does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the
previous values.
Clock Synchronous Communication Mode
Specify TE, RE, TEIE, TIE, RIE, and
Specify SDOS, SSCKOS, SCSOS,
Specify MSS and SCKS in SSCRH
Clear TE and RE bits in SSER to 0
Specify CPOS, CKS2, CKS1, and
CEIE bits in SSER simultaneously
Set SSUMS in SSCRL to 1 and
specify bits DATS1 and DATS0
TENDSTS, SCSATS, and
Start setting initial values
SSODTS bits in SSCR2
Set a bit in ICR to 1
CKS0 bits in SSMR
End
Section 14 Synchronous Serial Communication Unit (SSU)
[1] When the pin is used as an input.
[2] Specify master/slave mode selection and SSCK pin
[3] Selects clock synchronous communication mode and
[4] Specify clock polarity selection and transfer clock rate
[5] Enables/disables interrupt request to the CPU.
selection.
specify transmit/receive data length.
selection.
Rev. 3.00 Mar. 14, 2006 Page 539 of 804
REJ09B0104-0300