R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 217

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Writing to the registers for the channels when the corresponding DTE bit is set to 1 is prohibited
(except for the DTE bit). When changing the register settings after writing 0 to the DTE bit,
confirm that the DTE bit has been cleared to 0.
Figure 7.21 show the procedure for changing the register settings for the channel being
transferred.
(6)
The ACT bit in DMDR indicates whether the DMAC is in the idle or active state. When DTE = 0
or DTE = 1 and the DMAC is waiting for a transfer request, the ACT bit is 0. Otherwise (the
DMAC is in the active state), the ACT bit is 1. When individual transfers are stopped by writing 0
and the transfer is not completed, the ACT bit retains 1.
In block transfer mode, even if individual transfers are stopped by writing 0 to the DTE bit, the 1-
block size of transfers is not stopped. The ACT bit retains 1 from writing 0 to the DTE bit to
completion of a 1-block size transfer.
In burst mode, up to three times of DMA transfer are performed from the cycle in which the DTE
bit is written to 0. The ACT bit retains 1 from writing 0 to the DTE bit to completion of DMA
transfer.
Figure 7.21 Procedure for Changing Register Setting For Channel being Transferred
ACT Bit in DMDR
of channel during operation
Changing register settings
Change register settings
Write 0 to DTE bit
End of changing
register settings
Read DTE bit
DTE = 0?
Yes
No
[1]
[2]
[3]
[4]
[1] Write 0 to the DTE bit in DMDR.
[2] Read the DTE bit.
[3] Confirm that DTE = 0. DTE = 1
[4] Write the desired values to the
indicates that DMA is transferring.
registers.
Rev. 3.00 Mar. 14, 2006 Page 179 of 804
Section 7 DMA Controller (DMAC)
REJ09B0104-0300