R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 332

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 9 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Mar. 14, 2006 Page 294 of 804
REJ09B0104-0300
Bit
2
1
Bit Name
TGFC
TGFB
Initial
value
0
0
R/W
R/(W)* Input Capture/Output Compare Flag C
R/(W)* Input Capture/Output Compare Flag B
Status flag that indicates the occurrence of TGRC input
capture or compare match in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is a read-
only bit and cannot be modified.
[Setting conditions]
[Clearing conditions]
When 0 is written to TGFC after reading TGFC = 1
Status flag that indicates the occurrence of TGRB input
capture or compare match.
[Setting conditions]
[Clearing conditions]
Description
When TCNT = TGRC while TGRC is functioning as
output compare register
When TCNT value is transferred to TGRC by input
capture signal while TGRC is functioning as input
capture register
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
When TCNT = TGRB while TGRB is functioning as
output compare register
When TCNT value is transferred to TGRB by input
capture signal while TGRB is functioning as input
capture register
When 0 is written to TGFB after reading TGFB = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)

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