R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 33
R5F61525
Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5F61525.pdf
(846 pages)
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Section 1 Overview
Table 1.1
Table 1.2
Section 2 CPU
Table 2.1
Table 2.2
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Table 2.11
Table 2.12
Table 2.13
Table 2.14
Table 2.15
Section 3 MCU Operating Modes
Table 3.1
Table 3.2
Section 4 Exception Handling
Table 4.1
Table 4.2
Table 4.3
Table 4.4
Table 4.5
Table 4.6
Table 4.7
Table 4.8
Table 4.9
Section 5 Interrupt Controller
Table 5.1
Pin Configuration in Each Operating Mode.............................................................. 6
Pin Functions .......................................................................................................... 10
Instruction Classification ........................................................................................ 36
Combinations of Instructions and Addressing Modes (1)....................................... 38
Combinations of Instructions and Addressing Modes (2)....................................... 41
Operation Notation ................................................................................................. 42
Data Transfer Instructions....................................................................................... 43
Block Transfer Instructions..................................................................................... 44
Arithmetic Operation Instructions .......................................................................... 45
Logic Operation Instructions .................................................................................. 47
Shift Operation Instructions.................................................................................... 48
Bit Manipulation Instructions ................................................................................. 49
Branch Instructions ................................................................................................. 51
System Control Instructions.................................................................................... 52
Addressing Modes .................................................................................................. 54
Absolute Address Access Ranges ........................................................................... 58
Effective Address Calculation for Transfer and Operation Instructions ................. 62
Effective Address Calculation for Branch Instructions........................................... 63
MCU Operating Mode Settings .............................................................................. 67
Settings of Bits MSD3 to MSD0 ............................................................................ 69
Exception Types and Priority.................................................................................. 73
Exception Handling Vector Table........................................................................... 74
Calculation Method of Exception Handling Vector Table Address........................ 76
Status of CCR and EXR after Trace Exception Handling....................................... 78
Bus Cycle and Address Error.................................................................................. 79
States of CCR and EXR after Address Error Exception Handling ......................... 81
Interrupt Sources..................................................................................................... 81
Status of CCR and EXR after Trap Instruction Exception Handling...................... 83
Status of CCR and EXR after Illegal Instruction Exception Handling ................... 84
Pin Configuration.................................................................................................... 88
Tables
Rev. 3.00 Mar. 14, 2006 Page xxxiii of xxxviii
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