R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 227

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 7.31 shows an example of block transfer mode activated by the DREQ signal low level.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared. Receiving the next transfer request resumes after completion of the write cycle
and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is
completed.
Address bus
operation
Channel
[1]
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started.
[4][7] Transfer request enable is resumed after completion of the write cycle.
DREQ
DMA
B
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer
request is held.
(A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].)
Wait
Figure 7.31 Example of Transfer in Block Transfer Mode Activated
[1]
Request
Min. of 3 cycles
Bus released
[2]
Read
[3]
Duration of transfer
request disabled
DMA read
Transfer
source
cycle
1-block transfer
Write
by DREQ Low Level
Transfer request enable resumed
DMA write
destination
Transfer
cycle
Wait
[4]
Request
Min. of 3 cycles
Bus released
[5]
Rev. 3.00 Mar. 14, 2006 Page 189 of 804
Read
[6]
Section 7 DMA Controller (DMAC)
DMA read
Duration of transfer
request disabled
Transfer
cycle
source
1-block transfer
Write
Transfer request enable resumed
DMA write
destination
Transfer
cycle
Wait
REJ09B0104-0300
[7]
Bus released