R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 313

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 9.16 TIORL_0
[Legend]
X: Don't care
Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and Pφ/1 is used as the
Bit 7
IOD3
0
0
0
0
0
0
0
0
1
1
1
1
2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this
Bit 6
IOD2
0
0
0
0
1
1
1
1
0
0
0
1
TCNT_1 count clock, this setting is invalid and input capture is not generated.
setting is invalid and input capture/output compare is not generated.
Bit 5
IOD1
0
0
1
1
0
0
1
1
0
0
1
X
Bit 4
IOD0
0
1
0
1
0
1
0
1
0
1
X
X
TGRD_0
Function
Output
compare
register*
Input
capture
register*
2
2
TIOCD0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
Initial output is 0 output
Toggle output at compare match
Output disabled
Initial output is 1 output
0 output at compare match
Initial output is 1 output
1 output at compare match
Initial output is 1 output
Toggle output at compare match
Capture input source is TIOCD0 pin
Input capture at rising edge
Capture input source is TIOCD0 pin
Input capture at falling edge
Capture input source is TIOCD0 pin
Input capture at both edges
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down*
Rev. 3.00 Mar. 14, 2006 Page 275 of 804
Description
Section 9 16-Bit Timer Pulse Unit (TPU)
REJ09B0104-0300
1