R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 139

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.3.6
ISR is an IRQ14 to IRQ0 interrupt request register.
Note: *
Note:
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
*
Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should
be used to clear the flag.
IRQ Status Register (ISR)
Bit Name

IRQ14F
IRQ13F
IRQ12F
IRQ11F
IRQ10F
IRQ9F
IRQ8F
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
Only 0 can be written, to clear the flag. The bit manipulation instructions or memory
operation instructions should be used to clear the flag.
R/(W)*
R/(W)*
IRQ7F
15
—
0
7
0
IRQ14F
R/(W)*
R/(W)*
IRQ6F
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
14
0
6
0
IRQ13F
R/W
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
IRQ5F
13
0
5
0
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
[Setting condition]
•
[Clearing conditions]
•
•
•
IRQ12F
R/(W)*
R/(W)*
IRQ4F
12
0
4
0
When the interrupt selected by ISCR occurs
Writing 0 after reading IRQnF = 1
When interrupt exception handling is executed when
low-level sensing is selected and IRQn input is high
When IRQn interrupt exception handling is executed
when falling-, rising-, or both-edge sensing is
selected
IRQ11F
R/(W)*
R/(W)*
IRQ3F
11
0
3
0
Rev. 3.00 Mar. 14, 2006 Page 101 of 804
IRQ10F
R/(W)*
R/(W)*
IRQ2F
10
0
2
0
Section 5 Interrupt Controller
R/(W)*
R/(W)*
IRQ9F
IRQ1F
9
0
1
0
REJ09B0104-0300
R/(W)*
R/(W)*
IRQ8F
IRQ0F
8
0
0
0