R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 200

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
7.4.2
(1)
In normal transfer mode, one data access size of data is transferred at a single transfer request. Up
to 4 Gbytes can be specified as a total transfer size by DTCR. DBSR is ignored in normal transfer
mode.
The TEND signal is output only in the last DMA transfer.
Figure 7.7 shows an example of the signal timing in normal transfer mode and figure 7.8 shows
the operation in normal transfer mode.
Rev. 3.00 Mar. 14, 2006 Page 162 of 804
REJ09B0104-0300
Normal Transfer Mode
Address B
Address T
Transfer Modes
External request transfer in single address mode:
Auto request transfer in dual address mode:
Figure 7.7 Example of Signal Timing in Normal Transfer Mode
A
A
Bus cycle
TEND
DREQ
Bus cycle
DACK
Figure 7.8 Operations in Normal Transfer Mode
Read
DMA transfer
cycle
Write
Total transfer
size (DTCR)
Transfer
DMA
Read
Last DMA
transfer cycle
Write
DMA
Address T
Address B
B
B