R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 428

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Serial Communication Interface (SCI)
Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0):
Rev. 3.00 Mar. 14, 2006 Page 390 of 804
REJ09B0104-0300
Bit
7
6
Bit Name
TDRE
RDRF
Initial
Value
1
0
R/W
R/(W)* Transmit Data Register Empty
R/(W)* Receive Data Register Full
Description
Indicates whether TDR contains transmit data.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Indicates whether receive data is stored in RDR.
[Setting condition]
•
[Clearing conditions]
•
•
The RDRF flag is not affected and retains its previous
value when the RE bit in SCR is cleared to 0.
Note that when the next serial reception is completed
while the RDRF flag is being set to 1, an overrun error
occurs and the received data is lost.
When the TE bit in SCR is 0
When data is transferred from TDR to TSR
When 0 is written to TDRE after reading TDRE = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
When a TXI interrupt request is issued allowing
DMAC to write data to TDR
When serial reception ends normally and receive data
is transferred from RSR to RDR
When 0 is written to RDRF after reading RDRF = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
When an RXI interrupt request is issued allowing
DMAC to read data from RDR