R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 189

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
7.2.7
DACR specifies the operating mode and transfer method.
Bit
31
30
29 to 27 
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
DMA Address Control Register (DACR)
Bit Name
AMS
DIRS
SARIE
DARIE
AMS
R/W
R/W
R/W
31
23
15
R
0
0
0
7
0
Initial
Value
0
0
0
DIRS
R/W
30
22
14
R
R
R
0
0
0
6
0
R/W
R/W
R/W
R/W
SAT1
R/W
29
21
13
R
R
R
0
0
0
5
0
Description
Address Mode Select
Selects address mode from single or dual address
mode. In single address mode, the DACK pin is enabled
according to the DACKE bit.
0: Dual address mode
1: Single address mode
Single Address Direction Select
Specifies the data transfer direction in single address
mode. This bit s ignored in dual address mode.
0: Specifies DSAR as source address
1: Specifies DDAR as destination address
Reserved
These are read-only bits and cannot be modified.
SARA4
DARA4
SAT0
R/W
R/W
R/W
28
20
12
R
0
0
0
4
0
SARA3
DARA3
R/W
R/W
27
19
11
R
R
0
0
0
3
0
Rev. 3.00 Mar. 14, 2006 Page 151 of 804
DARA2
SARA2
Section 7 DMA Controller (DMAC)
RPTIE
R/W
R/W
R/W
26
18
10
R
0
0
0
2
0
SARA1
DARA1
ARS1
DAT1
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
REJ09B0104-0300
SARA0
DARA0
ARS0
DAT0
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0

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