R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 310

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 16-Bit Timer Pulse Unit (TPU)
9.3.3
TIOR controls TGR. The TPU has eight TIOR registers, two each for channels 0 and 3, and one
each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
To designate the input capture pin in TIOR, the DDR bit and ICR bit for the corresponding pin
should be set to 0 and 1, respectively. For details, see section 8, I/O Ports.
Note: The H8SX/1527 does not include TIOR_4 and TIOR_5.
• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5
• TIORL_0, TORL_3
Rev. 3.00 Mar. 14, 2006 Page 272 of 804
REJ09B0104-0300
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Timer I/O Control Register (TIOR)
IOB3
IOD3
R/W
R/W
7
0
7
0
IOD2
IOB2
R/W
R/W
6
0
6
0
IOB1
IOD1
R/W
R/W
5
0
5
0
IOD0
IOB0
R/W
R/W
4
0
4
0
IOA3
IOC3
R/W
R/W
3
0
3
0
IOA2
IOC2
R/W
R/W
2
0
2
0
IOC1
IOA1
R/W
R/W
1
0
1
0
IOA0
IOC0
R/W
R/W
0
0
0
0