R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 347

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(2)
(a)
Figure 9.16 shows an operation example in which PWM mode 1 has been designated for channel
0, and buffer operation has been designated for TGRA and TGRC. The settings used in this
example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at
compare match B.
As buffer operation has been set, when compare match A occurs, the output changes and the value
in buffer register TGRC is simultaneously transferred to timer general register TGRA. This
operation is repeated each time compare match A occurs.
For details on PWM modes, see section 9.4.5, PWM Modes.
Examples of Buffer Operation
When TGR is an output compare register
TGRB_0
TGRA_0
H'0000
TGRC_0
TGRA_0
TIOCA
TCNT value
Transfer
H'0200
H'0200
Figure 9.16 Example of Buffer Operation (1)
H'0200
H'0450
H'0450
H'0450
Rev. 3.00 Mar. 14, 2006 Page 309 of 804
Section 9 16-Bit Timer Pulse Unit (TPU)
H'0520
REJ09B0104-0300
H'0520
Time