R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 224

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
(3)
In block transfer mode, the bus is released every time a 1-block size of transfers at a single transfer
request is completed.
In figure 7.28, the TEND signal output is enabled and data is transferred in words from the
external 16-bit 2-state access space to the external 16-bit 2-state access space in block transfer
mode.
Rev. 3.00 Mar. 14, 2006 Page 186 of 804
REJ09B0104-0300
B
Address
bus
RD
LHWR,
LLWR
TEND
Block Transfer Mode
Bus
released
read cycle
DMA
Figure 7.28 Example of Transfer in Block Transfer Mode
write cycle
DMA
Block transfer
read cycle
DMA
write cycle
DMA
Bus
released
read cycle
DMA
write cycle
DMA
Last block transfer cycle
read cycle
DMA
write cycle
DMA
released
Bus