R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 164

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller (BSC)
6.2
The bus controller has the following registers.
• Bus control register 2 (BCR2)
6.2.1
BCR2 is used for bus arbitration control of the CPU and DMAC, and enabling/disabling of the
write data buffer function to the peripheral device.
Rev. 3.00 Mar. 14, 2006 Page 126 of 804
REJ09B0104-0300
Bit
7, 6
5
4
3, 2
1
0
Bit
Bit Name
Initial Value
R/W
Bit Name


IBCCS


PWDBE
Register Descriptions
Bus Control Register 2 (BCR2)
—
R
7
0
Initial
Value
All 0
0
0
All 0
1
0
—
R
6
0
R/W
R
R/W
R/W
R
R/W
R/W
R/W
—
5
0
Description
Reserved
These are read-only bits and cannot be modified.
Reserved
This bit is always read as 0. The write value should
always be 0.
Internal Bus Cycle Control Select
Selects the internal bus arbiter function.
0: Releases the bus mastership according to the priority
1: Executes the bus cycles alternatively when a CPU
Reserved
These are read-only bits and cannot be modified.
Reserved
This bit is always read as 1. The write value should
always be 1.
Peripheral Module Write Data Buffer Enable
Specifies whether or not to use the write data buffer
function for the peripheral module write cycles.
0: Write data buffer function not used
1: Write data buffer function used
bus mastership request conflicts with a DMAC bus
mastership request
IBCCS
R/W
4
0
—
R
3
0
—
R
2
0
R/W
—
1
1
PWDBE
R/W
0
0