R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 560
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R5F61525
Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5F61525.pdf
(846 pages)
- Current page: 560 of 846
- Download datasheet (6Mb)
Section 14 Synchronous Serial Communication Unit (SSU)
Rev. 3.00 Mar. 14, 2006 Page 522 of 804
REJ09B0104-0300
Bit
7
6
5
4
3
2
Bit Name
SDOS
SSCKOS
SCSOS
TENDSTS 0
SCSATS
SSODTS
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Serial Data Pin Open Drain Select
Selects whether the serial data output pin is used as a
CMOS or an NMOS open drain output. Pins to output
serial data differ according to the register setting. For
details, 14.4.3, Relationship between Data Input/Output
Pins and Shift Register.
0: CMOS output
1: NMOS open drain output
SSCK Pin Open Drain Select
Selects whether the SSCK pin is used as a CMOS or
an NMOS open drain output.
0: CMOS output
1: NMOS open drain output
SCS Pin Open Drain Select
Selects whether the SCS pin is used as a CMOS or an
NMOS open drain output.
0: CMOS output
1: NMOS open drain output
Selects the timing of setting the TEND bit (valid in SSU
and master mode).
0: Sets the TEND bit when the last bit is being
1: Sets the TEND bit after the last bit is transmitted
Selects the assertion timing of the SCS pin (valid in
SSU and master mode).
0: Min. values of t
1: Min. values of t
Selects the data output timing of the SSO pin (valid in
SSU and master mode)
0: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
1: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
transmitted
= 1, TE = 1, and RE = 0, the SSO pin outputs data
= 1, TE = 1, and RE = 0, the SSO pin outputs data
while the SCS pin is driven low
LEAD
LEAD
and t
and t
LAG
LAG
are 1/2 × t
are 3/2 × t
SUcyc
SUcyc
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