R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 94

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
2.8.4
The operand value is the contents of a memory location which is pointed to by the sum of the
following operation result and a 16- or 32-bit displacement: a specified bits of the contents of an
address register (RnL, Rn, ERn) specified by the register field in the instruction code are zero-
extended to 32-bit data and multiplied by 1, 2, or 4. The displacement is included in the instruction
code and the 16-bit displacement is sign-extended when added to ERn. If the operand is byte data,
ERn is multiplied by 1. If the operand is word or longword data, ERn is multiplied by 2 or 4,
respectively.
2.8.5
(1)
The operand value is the contents of a memory location which is pointed to by the contents of an
address register (ERn). ERn is specified by the register field of the instruction code. After the
memory location is accessed, 1, 2, or 4 is added to the address register contents and the sum is
stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for
longword access.
(2)
The operand value is the contents of a memory location which is pointed to by the following
operation result: the value 1, 2, or 4 is subtracted from the contents of an address register (ERn).
ERn is specified by the register field of the instruction code. After that, the operand value is stored
in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for
longword access.
(3)
The operand value is the contents of a memory location which is pointed to by the following
operation result: the value 1, 2, or 4 is added to the contents of an address register (ERn). ERn is
specified by the register field of the instruction code. After that, the operand value is stored in the
address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access.
Rev. 3.00 Mar. 14, 2006 Page 56 of 804
REJ09B0104-0300
Register indirect with post-increment—@ERn+
Register indirect with pre-decrement—@−ERn
Register indirect with pre-increment—@+ERn
Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B),
@(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)
Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment,
or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn−