R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 219

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.4.8
The channels of the DMAC are given following priority levels: channel 0 > channel 1 >
channel 2 > channel3. Table 7.5 shows the priority levels among the DMAC channels.
Table 7.5
The channel having highest priority other than the channel being transferred is selected when a
transfer is requested from other channels. The selected channel starts the transfer after the channel
being transferred releases the bus. At this time, when a bus master other than the DMAC requests
the bus, the cycle for the bus master is inserted.
In a burst transfer or a block transfer, channels are not switched.
Figure 7.22 shows a transfer example when multiple transfer requests from channels 0 to 2.
Channel
Channel 0
Channel 1
Channel 2
Channel 3
Address bus
Channel 0
Channel 1
Channel 2
DMAC
operation
B
Priority of Channels
Priority among DMAC Channels
Wait
Request
retained
Request
retained
Figure 7.22 Example of Timing for Channel Priority
Request cleared
Channel 0
Selected
Not
selected
Channel 0 transfer
Request
retained
Request cleared
Channel 0
Channel 1
Selected
Bus
released
Channel 1 transfer
Request cleared
Channel 1
Rev. 3.00 Mar. 14, 2006 Page 181 of 804
Channel 2
Section 7 DMA Controller (DMAC)
Bus
released
Channel 2 transfer
REJ09B0104-0300
Channel 2
Priority
High
Low
Wait