R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 401

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are
2. Write H'FF to NDERH, and set bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 in PCR to
3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs,
4. 4-phase complementary non-overlapping pulse output can be obtained subsequently by writing
output compare registers. Set the cycle in TGRB and the non-overlapping margin in TGRA,
and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to
enable the TGIA interrupt.
select compare match in the TPU channel set up in the previous step to be the output trigger.
Set bits G3NOV and G2NOV in PMR to 1 to select non-overlapping pulse output.
Write output data H'95 to NDRH.
outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0
to 1 (the change from 0 to 1 is delayed by the value set in TGRA).
The TGIA interrupt handling routine writes the next output data (H'65) to NDRH.
H'59, H'56, H'95... at successive TGIA interrupts.
If the DMAC is set for activation by a TGIA interrupt, pulse can be output without imposing a
load on the CPU.
Section 10 Programmable Pulse Generator (PPG)
Rev. 3.00 Mar. 14, 2006 Page 363 of 804
REJ09B0104-0300