R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 142

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Interrupt Controller
When the IRQ sensing control in ISCR is set to a low level of signal IRQn, the level of IRQn
should be held low until an interrupt handling starts. Then set the corresponding input signal IRQn
to high in the interrupt handling routine and clear the IRQnF to 0. Interrupts may not be executed
when the corresponding input signal IRQn is set to high before the interrupt handling begins.
5.4.2
The sources for internal interrupts from on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
• The interrupt priority can be set by means of IPR.
• The DMAC can be activated by a TPU, SCI, HCAN, SSU, or other interrupt request.
• DMAC activation can be controlled by the CPU priority control function over the DMAC.
Rev. 3.00 Mar. 14, 2006 Page 104 of 804
REJ09B0104-0300
IRQn input
[Legend]
n = 14 to 0
and enable bits that enable or disable these interrupts. They can be controlled independently.
When the enable bit is set to 1, an interrupt request is issued to the interrupt controller.
Corresponding bit
Internal Interrupts
Input buffer
in ICR
Figure 5.2 Block Diagram of Interrupts IRQn
IRQnSF, IRQnSR
detection circuit
Edge/level
Clear signal
R
S
IRQnF
Q
IRQnE
IRQn interrupt request