R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 188

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
Note:
Rev. 3.00 Mar. 14, 2006 Page 150 of 804
REJ09B0104-0300
Bit
2
1
0
*
Bit Name
DMAP2
DMAP1
DMAP0
Only 0 can be written to, to clear the flag.
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
DMA Priority Level 2 to 0
Select the priority level of the DMAC. When the CPU
has priority over the DMAC, the DMAC masks a transfer
request and waits for the timing when the CPU priority
becomes lower than the DMAC priority. The priority
levels can be set to the individual channels. This bit is
valid when the CPUPCE bit in CPUPCR is set to 1.
000: Priority level 0 (low)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (high)