R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 720

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 19 Power-Down Modes
19.7.3
Bits STS4 to STS0 in SBYCR should be set as described below.
1. Using a crystal resonator
2. Using an external clock
Table 19.2 Oscillation Settling Time Settings
Note:
Rev. 3.00 Mar. 14, 2006 Page 682 of 804
REJ09B0104-0300
STS4 STS3 STS2 STS1 STS0
0
1
Set bits STS4 to STS0 so that the standby time is at least equal to the oscillation settling time.
Table 19.2 shows the standby times for operating frequencies and settings of bits STS4 to
STS0.
A PLL circuit settling time is necessary. Refer to table 19.2 to set the standby time.
: Recommended time setting when using a crystal resonator.
: Recommended time setting when using an external clock.
0
1
0
*
Setting Oscillation Settling Time after Clearing Software Standby Mode
Pφ is the output from the peripheral module frequency divider.
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Standby
Time
Reserved 
Reserved 
Reserved 
Reserved 
Reserved 
64
512
1024
2048
4096
16384
32768
65536
131072
262144
524288
Reserved 
35
1.8
14.6
29.3
58.5
0.12
0.47
0.94
1.87
3.74
7.49
14.98
25
2.6
20.5
41.0
81.9
0.16
0.66
1.31
2.62
5.24
10.49
20.97
Pφ* [MHz]
20
3.2
25.6
51.2
102.4
0.20
0.82
1.64
3.28
6.55
13.11
26.21
Unit
µs
ms

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