DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1018

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 19 A/D Converter (ADC)
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Rev. 3.00 May 17, 2007 Page 960 of 1582
REJ09B0181-0300
Bit
3 to 0
Don't care
Bit Name
TRG0S[3:0]
Initial
Value
0000
R/W
R/W
Description
A/D Trigger 0 Select 3 to 0
Select an external trigger, MTU2 trigger, or MTU2S
trigger to start A/D conversion for A/D module 0. In 2-
channel scan mode, these bits select an external
trigger, MTU2 trigger, or MTU2S trigger to start A/D
conversion for group 0.
0000: External trigger pin (ADTRG) input
0001: TGRA input capture/compare match on each
0010: MTU2 CH0 compare match (TRG0N)
0011: MTU2 A/D conversion start request delaying
0100: MTU2 A/D conversion start request delaying
0101: TGRA input capture/compare match on each
0110: Setting prohibited
0111: MTU2S A/D conversion start request delaying
1000: MTU2S A/D conversion start request delaying
1001: Setting prohibited
101x: Setting prohibited
11xx: Setting prohibited
When switching the selector, first clear the ADST bit in
the A/D control register (ADCR) to 0.
Specify different trigger sources for the group 0 and
group 1 conversion requests so that a group 0
conversion request is not generated simultaneously
with a group 1 conversion request in 2-channel scan
mode.
MTU2 channel or TCNT_4 trough in
complementary PWM mode (TRGAN)
(TRG4AN)
(TRG4BN)
MTU2S channel or TCNT_4 trough in
complementary PWM mode (TRGAN)
(TRG4AN)
(TRG4BN)