DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1339

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

23.8.3
1. Download time of on-chip program
2. User branch processing intervals
Table 23.11 Initiation Intervals of User Branch Processing
However, when operation is done with CPU clock of 80 MHz, maximum values of the time until
first user branch processing are as shown in table 23.12.
Table 23.12 Initial User Branch Processing Time
3. Write to flash-memory related registers by DMAC or DTC
4. State in which interrupts are ignored
Processing Name
Programming
Erasing
Processing Name
Programming
Erasing
The programming program that includes the initialization routine and the erasing program that
includes the initialization routine are each 3 kbytes or less. Accordingly, when the CPU clock
frequency is 20 MHz, the download for each program takes approximately 10 ms at maximum.
The intervals for executing the user branch processing differs in programming and erasing. The
processing phase also differs. Table 23.11 lists the maximum intervals for initiating the user
branch processing when the CPU clock frequency is 80 MHz.
While an instruction in on-chip RAM is being executed, the DMAC or DTC can write to the
SCO bit in FCCS that is used for a download request or FMATS that is used for MAT
switching. Make sure that these registers are not accidentally written to, otherwise an on-chip
program may be downloaded and destroy RAM or a MAT switchover may occur and the CPU
get out of control.
In the following modes or period, interrupt requests are ignored; they are not executed and the
interrupt sources are not retained.
 Boot mode
 Programmer mode
Other Notes
Maximum Interval
Approximately 2 ms
Approximately 15 ms
Max.
Approximately 2 ms
Approximately 15 ms
Rev. 3.00 May 17, 2007 Page 1281 of 1582
Section 23 Flash Memory
REJ09B0181-0300