DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 437

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

output to the L bus and the rising edge of Bφ depends on the state of program execution. In the
case shown in the figure, where n = 0 and m = 0, the time required for access is 3 × Iφ + 1 × Bφ +
2 × Pφ.
Figure 9.53 shows an example of timing of read access to the peripheral bus when Iφ:Bφ:Pφ =
4:2:1. Transfer from the L bus to the peripheral bus is performed in the same way as for writing. In
the case of reading, however, values output onto the peripheral bus need to be transferred to the
CPU. Although transfers from the peripheral bus to the I bus and from the I bus to the L bus are
performed in synchronization with the rising edge of the respective bus clocks, a period of 2 × Iφ
is actually required because Iφ ≥ Bφ ≥ Pφ. In the case shown in the figure, where n = 0 and m = 1,
the time required for access is 3 × Iφ + 2 × Bφ + 2 × Pφ + 2 × Iφ.
Iφ
L bus
Bφ
I bus
Pφ
Peripheral bus
Figure 9.52 Timing of Write Access to On-Chip Peripheral I/O Registers
Figure 9.53 Timing of Read Access to On-Chip Peripheral I/O Registers
(3 + n) × Iφ
Iφ
L bus
Bφ
I bus
Pφ
Peripheral bus
(1 + m) × Bφ
(3 + n) × Iφ
When Iφ:Bφ:Pφ = 4:2:2
When Iφ:Bφ:Pφ = 4:2:1
(1 + m) × Bφ
2 × Pφ
2 × Pφ
Rev. 3.00 May 17, 2007 Page 379 of 1582
Section 9 Bus State Controller (BSC)
REJ09B0181-0300
2 × Iφ