DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 73

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Classification
Bus control
Symbol
CS8 to CS0
RD
RDWR
BS
AH
FRAME
WRHH
WRHL
WRH
WRL
WAIT
I/O
O
O
O
O
O
O
O
O
O
O
I
Name
Chip select 8 to 0 Chip-select signal for external
Read
Read/write
Bus start
Address hold
FRAME signal
Write to HH byte Indicates a write access to bits 31 to
Write to HL byte
Write to upper
byte
Write to lower
byte
Wait
Function
memory or devices.
CS7, CS3, and CS0 are available in
the SH7083.
CS7 to CS0 are available in the
SH7084/SH7085.
Indicates reading of data from
external devices.
Read/write signal
Bus-cycle start
Address hold timing signal for the
device that uses the address/data-
multiplexed bus.
Available only in the
SH7084/SH7085/SH7086.
In burst MPX-I/O interface mode,
negated before the last bus cycle to
indicate that the next bus cycle is the
last access.
Available only in the
SH7085/SH7086.
24 of the external data.
Available only in the
SH7085/SH7086.
Indicates a write access to bits 23 to
16 of the external data.
Available only in the
SH7085/SH7086.
Indicates a write access to bits 15 to
8 of the external data.
Indicates a write access to bits 7 to 0
of the external data.
Input signal for inserting a wait cycle
into the bus cycles during access to
the external space.
Rev. 3.00 May 17, 2007 Page 15 of 1582
Section 1 Overview
REJ09B0181-0300