DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 160

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 5 Exception Handling
5.8
5.8.1
The SP value must always be a multiple of 4. If it is not, an address error will occur when the
stack is accessed during exception handling.
5.8.2
The VBR value must always be a multiple of 4. If it is not, an address error will occur when the
stack is accessed during exception handling.
5.8.3
When the SP value is not a multiple of 4, an address error will occur when stacking for exception
handling (interrupts, etc.) and address error exception handling will start after the first exception
handling is ended. Address errors will also occur in the stacking for this address error exception
handling. To ensure that address error exception handling does not go into an endless loop, no
address errors are accepted at that point. This allows program control to be passed to the handling
routine for address error exception and enables error processing.
When an address error occurs during exception handling stacking, the stacking bus cycle (write) is
executed. When stacking the SR and PC values, the SP values for both are subtracted by 4,
therefore, the SP value is still not a multiple of 4 after the stacking. The address value output
during stacking is the SP value whose lower two bits are cleared to 0. So the write data stacked is
undefined.
Rev. 3.00 May 17, 2007 Page 102 of 1582
REJ09B0181-0300
Usage Notes
Value of Stack Pointer (SP)
Value of Vector Base Register (VBR)
Address Errors Caused by Stacking for Address Error Exception Handling