DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 303

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bit
29, 28
27
26, 25
24
23, 22
Bit Name
IWW[1:0]

IWRWD[1:0] 11

IWRWS[1:0] 11
Initial
Value
11
0
0
R/W
R/W
R
R/W
R
R/W
Description
Specification for Idle Cycles between Write-Read/Write-
Write Cycles
Specify the number of idle cycles to be inserted after
access to memory that is connected to the space. The
target cycles are write-read cycles and write-write
cycles.
00: No idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 4 idle cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
Specification for Idle Cycles between Read-Write
Cycles in Different Spaces
Specify the number of idle cycles to be inserted after
access to memory that is connected to the space. The
target cycles are continuous read-write cycles in
different spaces.
00: No idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 4 idle cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
Specification for Idle Cycles between Read-Write
Cycles in the Same Space
Specify the number of idle cycles to be inserted after
access to memory that is connected to the space. The
target cycles are continuous read-write cycles in the
same space.
00: No idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 4 idle cycles inserted
Rev. 3.00 May 17, 2007 Page 245 of 1582
Section 9 Bus State Controller (BSC)
REJ09B0181-0300