DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 14

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

9.5
Section 10 Direct Memory Access Controller (DMAC)................................... 383
10.1 Features.............................................................................................................................. 383
10.2 Input/Output Pins............................................................................................................... 385
10.3 Register Descriptions......................................................................................................... 386
10.4 Operation ........................................................................................................................... 397
Rev. 3.00 May 17, 2007 Page xiv of lviii
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
9.4.8
Operation ........................................................................................................................... 285
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
9.5.7
9.5.8
9.5.9
9.5.10 Burst MPX-I/O Interface ...................................................................................... 351
9.5.11 Burst ROM (Clock Synchronous) Interface.......................................................... 356
9.5.12 Wait between Access Cycles ................................................................................ 357
9.5.13 Bus Arbitration ..................................................................................................... 370
9.5.14 Others.................................................................................................................... 376
9.5.15 Access to On-Chip FLASH and On-Chip RAM by CPU ..................................... 378
9.5.16 Access to On-Chip Peripheral I/O Registers by CPU........................................... 378
9.5.17 Access to External Memory by CPU .................................................................... 380
10.3.1 DMA Source Address Registers_0 to _3 (SAR_0 to SAR_3) .............................. 387
10.3.2 DMA Destination Address Registers_0 to _3 (DAR_0 to DAR_3) ..................... 388
10.3.3 DMA Transfer Count Registers_0 to _3 (DMATCR_0 to DMATCR_3) ............ 388
10.3.4 DMA Channel Control Registers_0 to _3 (CHCR_0 to CHCR_3) ...................... 389
10.3.5 DMA Operation Register (DMAOR) ................................................................... 394
10.3.6 Bus Function Extending Register (BSCEHR) ...................................................... 396
10.4.1 DMA Transfer Flow ............................................................................................. 397
10.4.2 DMA Transfer Requests ....................................................................................... 399
Common Control Register (CMNCR) .................................................................. 242
CSn Space Bus Control Register (CSnBCR) (n = 0 to 8) ..................................... 244
CSn Space Wait Control Register (CSnWCR) (n = 0 to 8) .................................. 249
SDRAM Control Register (SDCR)....................................................................... 272
Refresh Timer Control/Status Register (RTCSR)................................................. 275
Refresh Timer Counter (RTCNT)......................................................................... 277
Refresh Time Constant Register (RTCOR) .......................................................... 278
Bus Function Extending Register (BSCEHR) ...................................................... 279
Endian/Access Size and Data Alignment.............................................................. 285
Normal Space Interface ........................................................................................ 288
Access Wait Control ............................................................................................. 294
CSn Assert Period Extension ................................................................................ 296
MPX-I/O Interface................................................................................................ 297
SDRAM Interface ................................................................................................. 301
Burst ROM (Clock Asynchronous) Interface ....................................................... 337
SRAM Interface with Byte Selection ................................................................... 339
PCMCIA Interface................................................................................................ 344