DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 266

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 8 Data Transfer Controller (DTC)
Rev. 3.00 May 17, 2007 Page 208 of 1582
REJ09B0181-0300
Clock (Bφ)
DTC activation
request 1
DTC activation
request 2
DTC request
Bus release timing
[setting 5]
Bus release timing
[setting 3]
Bus release timing
[setting 4]
Bus release timing
[setting 1]
Bus release timing
[setting 2]
[Legend]
Note: DTC request signal indicates the state of internal bus request after the DTC activation source is determined.
Internal address
: Indicates bus release timing.
: Bus mastership is only released for the external access request from the CPU.
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
(Activated by On-Chip Peripheral Module; Iφ: Bφ: Pφ = 1: 1/2: 1/2;
Conflict of Two Activation Requests in Normal Transfer Mode
Vector
read
Figure 8.16 Example of DTC Operation Timing:
Transfer Information is Written in 3 Cycles)
Transfer information
read
transfer
Data
R
Transfer information
W
write
Vector
read
Transfer information
read
transfer
Data
R
Transfer information
W
write