DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 243

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Start address
transfer
Chain
Figure 8.3 Correspondence between DTC Vector Address and Transfer Information
Configuration of transfer information
MRA
MRA
0
Upper: DTCVBR
Lower: H'400 + vector number × 4
in normal address mode
CRA
CRA
Lower addresses
MRB
MRB
1
4 bytes
SAR
DAR
SAR
DAR
DTC vector
address
2
Reserved
Reserved
(0 write)
(write 0)
Figure 8.2 Transfer Information on Data Area
CRB
CRB
+4n
+4
3
Transfer information for
one round of transfer
(4 longwords)
Transfer information for
the 2nd round of transfer
in chain transfer
(4 longwords)
Transfer information (1)
Transfer information (2)
Transfer information (n)
start address
start address
start address
Vector table
4 bytes
:
:
:
Start address
Note: Since the upper 8 bits of SAR and DAR are regarded as all 1,
transfer
Chain
short address mode can be set only for transfer
between on-chip peripheral modules and on-chip RAM.
Configuration of transfer information
MRA
MRB
MRA
MRB
Rev. 3.00 May 17, 2007 Page 185 of 1582
0
Section 8 Data Transfer Controller (DTC)
in short address mode
CRA
CRA
Lower addresses
1
4 bytes
Transfer information (1)
Transfer information (2)
Transfer information (n)
SAR
DAR
SAR
DAR
2
CRB
CRB
:
:
:
3
REJ09B0181-0300
Transfer information for
one round of transfer
(3 longwords)
Transfer information for
the 2nd round of transfer
in chain transfer
(3 longwords)