DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 966

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 18 I
18.3.2
ICCR2 is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA
pin, monitors the SCL pin, and controls reset in the control part of the I
Rev. 3.00 May 17, 2007 Page 908 of 1582
REJ09B0181-0300
Bit
7
6
I
2
Bit Name
BBSY
SCP
2
C Bus Control Register 2 (ICCR2)
C Bus Interface 2 (I
Initial value:
Initial
Value
0
1
R/W:
Bit:
2
C2)
BBSY
R/W
7
0
R/W
R/W
R/W
R/W
SCP
6
1
Description
Bus Busy
This bit enables to confirm whether the I
occupied or released and to issue start/stop conditions
in master mode. With the clock synchronous serial
format, this bit is always read as 0. With the I
format, this bit is set to 1 when the SDA level changes
from high to low under the condition of SCL = high,
assuming that the start condition has been issued. This
bit is cleared to 0 when the SDA level changes from low
to high under the condition of SCL = high, assuming
that the stop condition has been issued. Write 1 to
BBSY and 0 to SCP to issue a start condition. Follow
this procedure also when transmitting a repeated start
condition. Write 0 in BBSY and 0 in SCP to issue a stop
condition.
Start/Stop Issue Condition Disable
The SCP bit controls the issue of start/stop conditions in
master mode.
To issue a start condition, write 1 in BBSY and 0 in
SCP. A repeated start condition is issued in the same
way. To issue a stop condition, write 0 in BBSY and 0 in
SCP. This bit is always read as 1. Even if 1 is written to
this bit, the data will not be stored.
SDAO SDAOP SCLO
R/W
5
1
R/W
4
1
R
3
1
R
2
1
-
IICRST
R/W
1
0
2
C bus interface 2.
R
0
1
-
2
C bus is
2
C bus