DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1021

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

19.4.3
In single-cycle scan mode, A/D conversion is to be performed once on the specified channels (up
to four channels in SH7083/SH7084/SH7085 and up to eight channels in SH7086).
1. When the ADST bit in ADCR is set to 1 by a software, MTU2, MTU2S, or external trigger
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
4. After A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter
19.4.4
The A/D converter has a built-in sample-and-hold circuit for each module. The A/D converter
samples the analog input when the A/D conversion start delay time (t
bit in ADCR is set to 1, then starts conversion. Figure 19.2 shows the A/D conversion timing.
Table 19.4 shows the A/D conversion time.
As indicated in figure 19.2, the A/D conversion time (t
(t
conversion time therefore varies within the ranges indicated in table 19.4.
In scan mode, the values given in table 19.4 apply to the first conversion time. The values given in
table 19.5 apply to the second and subsequent conversions.
SPL
input, A/D conversion starts on the channel with the lowest number in the group (AN0, AN1,
..., AN7).
the A/D data register corresponding to each channel.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends.
enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D
conversion stops and the A/D converter enters the idle state.
). The length of t
Single-Cycle Scan Mode
Input Sampling and A/D Conversion Time
D
varies depending on the timing of the write access to ADCR. The total
CONV
) includes t
Rev. 3.00 May 17, 2007 Page 963 of 1582
Section 19 A/D Converter (ADC)
D
D
) has passed after the ADST
and the input sampling time
REJ09B0181-0300