DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 363

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
Address Multiplexing: An address multiplexing is specified so that SDRAM can be connected
without external address multiplexing circuitry according to the setting of bits BSZ[1:0] in
CSnBCR, and AxROW[1:0] and AxCOL[1:0] in SDCR. Tables 9.20 to 9.25 show the relationship
between the settings of bits BSZ[1:0], AxROW[1:0], and AxCOL[1:0] and the bits output at the
address pins. Do not specify those bits in the manner other than this table, otherwise the operation
of this LSI is not guaranteed. A25 to A18 are not multiplexed and the original values of address
are always output at these pins.
When the data bus width is 16 bits (BSZ[1:0] = B'10), the A0 pin of SDRAM specifies a word
address. Therefore, connect this A0 pin of SDRAM to the A1 pin of this LSI, then A1 pin to the
A2 pin, and so on. When the data bus width is 32 bits (BSZ[1:0] = B'11), the A0 pin of SDRAM
specifies a longword address. Therefore, connect this A0 pin of SDRAM to the A2 pin of this LSI,
then A1 pin to the A3 pin, and so on.
Rev. 3.00 May 17, 2007 Page 305 of 1582
REJ09B0181-0300