DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 886

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.12 Line Status Register (SCLSR)
SCLSR is a 16-bit readable/writable register which can always be read from and written to by the
CPU. However, a 1 cannot be written to the ORER flag. This flag can be cleared to 0 only if it has
first been read (after being set to 1).
Initial value:
Rev. 3.00 May 17, 2007 Page 828 of 1582
REJ09B0181-0300
Bit
15 to 1
0
Note:
R/W:
Bit:
*
To clear the flag, only 0 can be written after reading 1.
15
R
0
-
Bit Name

ORER
14
R
0
-
13
R
0
-
Initial
value
All 0
0
12
R
0
-
11
R
0
-
R/W
R
R/(W)* Overrun Error
10
R
0
-
R
9
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Indicates the occurrence of an overrun error.
0: Receiving is in progress or has ended normally *
[Clearing conditions]
•
•
1: An overrun error has occurred *
[Setting condition]
•
Notes: 1. Clearing the RE bit to 0 in SCSCR does
-
ORER is cleared to 0 when the chip is a power-on
reset
ORER is cleared to 0 when 0 is written after 1 is
read from ORER.
ORER is set to 1 when the next serial receiving is
finished while receive FIFO data are full.
R
8
0
-
2. The receive FIFO data register (SCFRDR)
R
7
0
-
not affect the ORER bit, which retains its
previous value.
hold the data before an overrun error is
occurred, and the next receive data is
extinguished. When ORER is set to 1,
SCIF can not continue the next serial
receiving.
R
6
0
-
R
5
0
-
R
4
0
-
R
3
0
-
2
R
2
0
-
R
1
0
-
R/(W)*
ORER
0
0
1