DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 628

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 3.00 May 17, 2007 Page 570 of 1582
REJ09B0181-0300
Figure 11.57 Example of Procedure for Setting Output Waveform Control at Synchronous
 Example of Procedure for Setting Output Waveform Control at Synchronous Counter
 Examples of Output Waveform Control at Synchronous Counter Clearing in
Clearing in Complementary PWM Mode
An example of the procedure for setting output waveform control at synchronous counter
clearing in complementary PWM mode is shown in figure 11.57.
Complementary PWM Mode
Figures 11.58 to 11.61 show examples of output waveform control in which the MTU2
operates in complementary PWM mode and synchronous counter clearing is generated
while the WRE bit in TWCR is set to 1. In the examples shown in figures 11.58 to 11.61,
synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 11.56,
respectively.
In the MTU2S, these examples are equivalent to the cases when the MTU2S operates in
complementary PWM mode and synchronous counter clearing is generated while the SCC
bit is cleared to 0 and the WRE bit is set to 1 in TWCR.
synchronous counter clearing
synchronous counter clearing
Output waveform control at
complementary PWM mode
Output waveform control at
Stop count operation
Start count operation
Set TWCR and
Counter Clearing in Complementary PWM Mode
[1]
[2]
[3]
[1] Clear bits CST3 and CST4 in the timer
[2] Read bit WRE in TWCR and then write 1
[3] Set bits CST3 and CST4 in TSTR to 1 to
start register (TSTR) to 0, and halt timer
counter (TCNT) operation. Perform
TWCR setting while TCNT_3 and
TCNT_4 are stopped.
to it to suppress initial value output at
counter clearing.
start count operation.