DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 189

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 6.4
Notes: *
Item
DMAC/DTC active
judgement
Interrupt priority decision
and comparison with mask
bits in SR
Wait for completion of
sequence currently being
executed by CPU
Time from start of interrupt
exception handling until
fetch of first instruction of
exception handling routine
starts
Interrupt
response
time
In the case that m1 = m2 = m3 = m4 = 1 × Icyc.
m1 to m4 are the number of cycles needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
Interrupt Response Time
Minimum*:
Maximum:
Total:
NMI

1 × Icyc + 2 ×
Pcyc
X (≥ 0)
8 × Icyc +
m1 + m2 + m3
9 × Icyc + 2 ×
Pcyc + m1 + m2
+ m3 + X
12 × Icyc +
2 × Pcyc
16 × Icyc +
2 × Pcyc + 2 ×
(m1 + m2 + m3)
+ m4
Number of Cycles
IRQ
2 × Bcyc
1 × Icyc + 1 ×
Pcyc
X (≥ 0)
8 × Icyc +
m1 + m2 + m3
9 × Icyc + 1 ×
Pcyc +2 × Bcyc +
m1 + m2 + m3 +
X
12 × Icyc +
1 × Pcyc +
2 × Bcyc
16 × Icyc +
1 × Pcyc +
2 × Bcyc + 2 ×
(m1 + m2 + m3)
+ m4
Peripheral
Modules
1 × Pcyc
1 × Icyc + 2 ×
Pcyc
X (≥ 0)
8 × Icyc +
m1 + m2 + m3
9 × Icyc + 3 ×
Pcyc + m1 + m2
+ m3 + X
12 × Icyc +
3 × Pcyc
16 × Icyc +
3 × Pcyc + 2 ×
(m1 + m2 + m3)
+ m4
Rev. 3.00 May 17, 2007 Page 131 of 1582
Section 6 Interrupt Controller (INTC)
Remarks
The longest sequence is
for interrupt or address-
error exception handling
(X = 7 × Icyc + m1 + m2
+ m3 + m4). If an
interrupt-masking
instruction follows,
however, the time may
be even longer.
Performs the saving PC
and SR, and vector
address fetch.
SR, PC, and vector table
are all in on-chip RAM.
REJ09B0181-0300