DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1606

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Rev. 3.00 May 17, 2007 Page 1548 of 1582
REJ09B0181-0300
Item
9.4.2 CSn Space Bus Control
Register (CSnBCR) (n = 0 to 8)
9.4.8 Bus Function Extending
Register (BSCEHR)
9.5.13 Bus Arbitration
Page Revision (See Manual for Details)
247
282
374
376
Added
Added
Added
When the SDRAM interface is used, an all bank
precharge command (PALL) is issued if any active
banks exist and releases the bus after completion of the
PALL command.
Processing by this LSI continues even while bus
mastership is released to an external device, unless an
external device is accessed. When an external device is
accessed, the LSI enters the state of waiting for bus
mastership to be returned.
Added
Acceptance of mastership for the DMAC in bus
arbitration takes 1Bφ, so a NOP 1Bφ in duration is
inserted on the I bus.
Acceptance of mastership for the DTC in bus arbitration
does not require the insertion of a NOP, so bus access
proceeds continuously.
Bit
14 to 12
Bit Bit Name Description
9
CSSTP3
Bit Name
TYPE[2:0] Memory Type Specification
Select Priority for External Memory Access by CPU
…….
Note: When this bit is 0, and access to internal I/O
from the CPU is immediately followed by
access to external space from the CPU, a
NOP 1Bφ in duration is inserted between the
two access cycles.
Description
…….
Notes: 2. SDRAM can be selected only for
areas 2 and 3. If the SDRAM is
only to be connected in one area,
select area 3 as the SDRAM
space. In this case, specify area 2
as normal space or SRAM with
byte selection.