DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 36

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Figure 11.107 Transfer Timing from Buffer Register to Temporary Register
Figure 11.108 Transfer Timing from Temporary Register to Compare Register ....................... 616
Figure 11.109 TGI Interrupt Timing (Compare Match) (Channels 0 to 4)................................. 617
Figure 11.110 TGI Interrupt Timing (Compare Match) (Channel 5) ......................................... 617
Figure 11.111 TGI Interrupt Timing (Input Capture) (Channels 0 to 4)..................................... 618
Figure 11.112 TGI Interrupt Timing (Input Capture) (Channel 5) ............................................. 618
Figure 11.113 TCIV Interrupt Setting Timing............................................................................ 619
Figure 11.114 TCIU Interrupt Setting Timing............................................................................ 619
Figure 11.115 Timing for Status Flag Clearing by CPU (Channels 0 to 4)................................ 620
Figure 11.116 Timing for Status Flag Clearing by CPU (Channel 5) ........................................ 620
Figure 11.117 Timing for Status Flag Clearing by DTC Activation (Channels 0 to 4) .............. 621
Figure 11.118 Timing for Status Flag Clearing by DTC Activation (Channel 5)....................... 621
Figure 11.119 Timing for Status Flag Clearing by DMAC Activation ...................................... 622
Figure 11.120 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode .............. 623
Figure 11.121 Contention between TCNT Write and Clear Operations..................................... 624
Figure 11.122 Contention between TCNT Write and Increment Operations ............................. 625
Figure 11.123 Contention between TGR Write and Compare Match......................................... 626
Figure 11.124 Contention between Buffer Register Write and Compare Match........................ 627
Figure 11.125 Contention between Buffer Register Write and TCNT Clear.............................. 628
Figure 11.126 Contention between TGR Read and Input Capture (Channels 0 to 4)................. 629
Figure 11.127 Contention between TGR Read and Input Capture (Channel 5) ......................... 629
Figure 11.128 Contention between TGR Write and Input Capture (Channels 0 to 4)................ 630
Figure 11.129 Contention between TGR Write and Input Capture (Channel 5) ........................ 630
Figure 11.130 Contention between Buffer Register Write and Input Capture............................ 631
Figure 11.131 TCNT_2 Write and Overflow/Underflow Contention with Cascade
Figure 11.132 Counter Value during Complementary PWM Mode Stop................................... 633
Figure 11.133 Buffer Operation and Compare-Match Flags in Reset Synchronous PWM
Figure 11.134 Reset Synchronous PWM Mode Overflow Flag ................................................. 635
Figure 11.135 Contention between Overflow and Counter Clearing ......................................... 636
Figure 11.136 Contention between TCNT Write and Overflow................................................. 637
Figure 11.137 Error Occurrence in Normal Mode, Recovery in Normal Mode ......................... 642
Figure 11.138 Error Occurrence in Normal Mode, Recovery in PWM Mode 1......................... 643
Figure 11.139 Error Occurrence in Normal Mode, Recovery in PWM Mode 2......................... 644
Figure 11.140 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode ............ 645
Figure 11.141 Error Occurrence in Normal Mode, Recovery in Complementary PWM
Rev. 3.00 May 17, 2007 Page xxxvi of Iviii
(TCNTS Operating)............................................................................................. 616
Mode.................................................................................................................... 634
Mode.................................................................................................................... 646
Connection .......................................................................................................... 632