DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1042

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 20 Compare Match Timer (CMT)
20.5.4
Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the byte-writing
has priority over the count-up. In this case, the count-up is not performed. The byte data on
another side, which is not written to, is also not counted and the previous contents remain.
Figure 20.7 shows the timing when the count-up occurs in the T2 cycle while writing to CMCNT
in bytes.
20.5.5
Do not set the same value in CMCNT and CMCOR while CMCNT is not counting. If set, the
CMF bit in CMCSR is set to 1 and CMCNT is cleared to H'0000.
Rev. 3.00 May 17, 2007 Page 984 of 1582
REJ09B0181-0300
Figure 20.7 Conflict between Byte-Write and Count-Up Processes of CMCNT
Conflict between Byte-Write and Count-Up Processes of CMCNT
Compare Match between CMCNT and CMCOR
Peripheral operating
CMCNT count-up
Internal write
clock (Pφ)
CMCNTH
CMCNTL
Address
enable
CMCSR write cycle
X
N
T1
CMCNTH
T2
M (CMCNT write data)
X