DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 87

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

2.3.3
Immediate data of eight bits is placed in the instruction code.
For the MOV, ADD, and CMP/EQ instructions, the immediate data is sign-extended to longword
and then calculated. For the TST, AND, OR, and XOR instructions, the immediate data is zero-
extended to longword and then calculated. Thus, if the immediate data is used for the AND
instruction, the upper 24 bits in the destination register are always cleared.
The immediate data of word or longword is not placed in the instruction code. It is placed in a
table in memory. The table in memory is accessed by the MOV immediate data instruction in PC
relative addressing mode with displacement.
2.4
2.4.1
The instructions are RISC-type instructions with the following features:
Fixed 16-Bit Length: All instructions have a fixed length of 16 bits. This improves program code
efficiency.
One Instruction per Cycle: Since pipelining is used, basic instructions can be executed in one
cycle.
Data Size: The basic data size for operations is longword. Byte, word, or longword can be
selected as the memory access size. Byte or word data in memory is sign-extended to longword
and then calculated. Immediate data is sign-extended to longword for arithmetic operations or
zero-extended to longword size for logical operations.
Table 2.2
Note:
CPU in this LSI
MOV.W
ADD
.DATA.W H'1234
*
Immediate Data Formats
Features of Instructions
RISC Type
Immediate data is accessed by @(disp,PC).
@(disp,PC),R1
R1,R0
........
Word Data Sign Extension
Description
Sign-extended to 32 bits, R1
becomes H'00001234, and is
then operated on by the ADD
instruction.
Rev. 3.00 May 17, 2007 Page 29 of 1582
Example of Other CPUs
ADD.W #H'1234,R0
REJ09B0181-0300
Section 2 CPU