DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 219

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

7.4.4
1. By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break
2. In sequential break specification, the L or I bus can be selected and the execution times break
7.4.5
When a user break occurs, the address of the instruction from where execution is to be resumed is
saved in the stack, and the exception handling state is entered. If the L bus is specified as a break
condition, the instruction at which the user break should occur can be clearly determined (except
for when data is included in the break condition). If the I bus is specified as a break condition, the
instruction at which the user break should occur cannot be clearly determined.
1. When instruction fetch (before instruction execution) is specified as a break condition:
2. When instruction fetch (after instruction execution) is specified as a break condition:
break occurs at a delayed branch instruction or its delay slot, the user break may not actually
take place until the first instruction at the branch destination.
condition matches after a channel A break condition matches. A user break is not generated
even if a channel B break condition matches before a channel A break condition matches.
When channels A and B conditions match at the same time, the sequential break is not issued.
To clear the channel A condition match when a channel A condition match has occurred but a
channel B condition match has not yet occurred in a sequential break specification, clear the
SEQ bit in BRCR to 0 and clear the condition match flag to 0 in channel A.
condition can be also specified. For example, when the execution times break condition is
specified, the break condition is satisfied when a channel B condition matches with BETR =
H'0001 after a channel A condition has matched.
The address of the instruction that matched the break condition is saved in the stack. The
instruction that matched the condition is not executed, and the user break occurs before it.
However when a delay slot instruction matches the condition, the address of the delayed
branch instruction is saved in the stack.
The address of the instruction following the instruction that matched the break condition is
saved in the stack. The instruction that matches the condition is executed, and the user break
occurs before the next instruction is executed. However when a delayed branch instruction or
delay slot matches the condition, these instructions are executed, and the branch destination
address is saved in the stack.
Sequential Break
Value of Saved Program Counter
Rev. 3.00 May 17, 2007 Page 161 of 1582
Section 7 User Break Controller (UBC)
REJ09B0181-0300