DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 95

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Instruction Format
nm type
15
md type
15
nd4 type
15
nmd type
15
xxxx nnnn mmmm xxxx
xxxx xxxx mmmm dddd
xxxx xxxx nnnn dddd
xxxx nnnn mmmm dddd
0
0
0
0
Source Operand
mmmm: register
direct
mmmm: register
direct
mmmm: post-
increment register
indirect (multiply-
and-accumulate
operation)
nnnn: * post-
increment register
indirect (multiply-
and-accumulate
operation)
mmmm: post-
increment register
indirect
mmmm: register
direct
mmmm: register
direct
mmmmdddd:
register indirect
with displacement
R0 (register direct) nnnndddd:
mmmm: register
direct
mmmmdddd:
register indirect
with displacement
Destination
Operand
nnnn: register
direct
nnnn: register
indirect
MACH, MACL
nnnn: register
direct
nnnn: pre-
decrement register
indirect
nnnn: index
register indirect
R0 (register direct) MOV.B @(disp,Rm),R0
register indirect
with displacement
nnnndddd:
register indirect
with displacement
nnnn: register
direct
Rev. 3.00 May 17, 2007 Page 37 of 1582
Sample Instruction
ADD
MOV.L Rm,@Rn
MAC.W @Rm+,@Rn+
MOV.L @Rm+,Rn
MOV.L Rm,@-Rn
MOV.L Rm,@(R0,Rn)
MOV.B R0,@(disp,Rn)
MOV.L Rm,@(disp,Rn)
MOV.L @(disp,Rm),Rn
Rm,Rn
REJ09B0181-0300
Section 2 CPU